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CY7C342B
128-Macrocell MAX(R) EPLD
Features
* 128 macrocells in eight logic array blocks (LABs) * Eight dedicated inputs, 52 bidirectional I/O pins * Programmable interconnect array * Advanced 0.65-micron CMOS technology to increase performance * Available in 68-pin HLCC, PLCC, and PGA packages 100% user-configurable, allowing the device to accommodate a variety of independent logic functions. The 128 macrocells in the CY7C342B are divided into eight LABs, 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C342B allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the functionality of 20-pin PLDs, the CY7C342B allows the replacement of over 50 TTL devices. By replacing large amounts of logic, the CY7C342B reduces board space, part count, and increases system reliability.
Functional Description
The CY7C342B is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX(R) architecture is
Logic Block Diagram
1 (B6) 2 (A6) 32 (L4) 34 (L5) INPUT/CLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT (A7) (A8) (L6) (K6) 68 66 36 35
SYSTEM CLOCK LAB A MACROCELL 1 MACROCELL 2 MACROCELL 3 MACROCELL 4 MACROCELL 5 MACROCELL 6 MACROCELL 7 MACROCELL 8 MACROCELL 9-16 LAB B MACROCELL 17 MACROCELL 18 MACROCELL 19 MACROCELL 20 MACROCELL 21 MACROCELL 22-32 P I A LAB H MACROCELL 120 MACROCELL 119 MACROCELL 118 MACROCELL 117 MACROCELL 116 MACROCELL 115 MACROCELL 114 MACROCELL 113 MACROCELL 121-128 LAB G MACROCELL 101 MACROCELL 100 MACROCELL 99 MACROCELL 98 MACROCELL 97 MACROCELL 102-112 (B8) 65 (A9) 64 (B9) 63 (A10) 62 (B10) 61 (B11) 60 (C11) 59 (C10) 58
4 (A5) 5 (B4) 6 (A4) 7 (B3) 8 (A3) 9 (A2) 10 (B2) 11 (B1)
12 (C2) 13 (C1) 14 (D2) 15 (D1) 17 (E1)
(D11) 57 (D10) 56 (E11) 55 (F11) 53 (F10) 52
18 (F2) 19 (F1) 21 (G1) 22 (H2) 23 (H1)
LAB C MACROCELL 33 MACROCELL 34 MACROCELL 35 MACROCELL 36 MACROCELL 37 MACROCELL 38-48
LAB F MACROCELL 85 MACROCELL 84 MACROCELL 83 MACROCELL 82 MACROCELL 81 MACROCELL 86-96
(G11) 51 (H11) 49 (H10) 48 (J11) 47 (J10) 46
24 (J2) 25 (J1) 26 (K1) 27 (K2) 28 (L2) 29 (K3) 30 (L3) 31 (K4)
LAB D MACROCELL 49 MACROCELL 50 MACROCELL 51 MACROCELL 52 MACROCELL 53 MACROCELL 54 MACROCELL 55 MACROCELL 56 MACROCELL 57-64 3, 20, 37, 54 (B5, G2, K7, E10) 16, 33, 50, 67 (E2, K5, G10, B7) VCC GND
LAB E MACROCELL 72 MACROCELL 71 MACROCELL 70 MACROCELL 69 MACROCELL 68 MACROCELL 67 MACROCELL 66 MACROCELL 65 MACROCELL 73-80
(K11) 45 (K10) 44 (L10) 43 (L9) 42 (K9) 41 (L8) 40 (K8) 39 (L7) 38
() - PERTAIN TO 68-PIN PGA PACKAGE
Cypress Semiconductor Corporation Document #: 38-03014 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised April 22, 2004
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Selection Guide
7C342B-15 Maximum Access Time 15 7C342B-20 20 7C342B-25 25 7C342B-30 30
CY7C342B
7C342B-35 35
Unit ns
Pin Configurations
HLCC, PLCC Top View
INPUT/CLK INPUT
PGA Bottom View
V CC INPUT
INPUT
L I/O I/O I/O I/O I/O
I/O
I/O
INPUT INPUT INPUT
I/O
I/O
I/O
I/O
GND
I/O I/O
I/O
I/O
I/O
I/O
K 9 I/O I/O I/O I/O I/O I/O GND I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O 10 11 12 13 14 15 16 17 18 19 20 21 22 23 7C342B 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O GND I/O I/O I/O I/O I/O I/O C J
I/O
I/O
I/O
I/O
GND
INPUT
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
H
I/O
I/O
I/O
I/O
G
I/O
VCC
GND
I/O
F
I/O
I/O
7C342B
I/O
I/O
E
I/O
GND
VCC
I/O
D
I/O
I/O
I/O
I/O
24 45 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 4344 INPUT INPUT INPUT V CC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O INPUT I/O
I/O
I/O INPUT/ GND CLK
I/O
I/O
B
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
A 1
I/O
I/O
I/O
I/O
INPUT INPUT INPUT
I/O
I/O
2
3
4
5
6
7
8
9
10
11
Document #: 38-03014 Rev. *B
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Logic Array Blocks
There are eight logic array blocks in the CY7C342B. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the macrocell array. All I/O feedbacks go to the programmable interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in which they are situated. Externally, the CY7C342B provides eight dedicated inputs, one of which may be used as a system clock. There are 52 I/O pins that may be individually configured for input, output, or bidirectional data flow.
CY7C342B
placement and routing iterations required for a programmable gate array to achieve design timing objectives.
Timing Delays
Timing delays within the CY7C342B may be easily determined using Warp(R), Warp ProfessionalTM, or Warp EnterpriseTM software by the model shown in Figure 1. The CY7C342B has fixed internal delays, allowing the user to determine the worst-case timing delays for any design.
Design Recommendations
Operation of the devices described herein with conditions above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C342B contains circuitry to protect device pins from high static voltages or electric fields, but normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages. For proper operation, input and output pins must be constrained to the range GND < (VIN or VOUT) < VCC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 F must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types have.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This eliminates undesired skews among logic signals that may cause glitches in internal or external logic. The fixed delay, regardless of programmable interconnect array configuration, simplifies design by assuring that internal signal skews or races are avoided. The result is ease of design implementation, often in a signal pass, without the multiple internal logic
EXPANDER DELAY tEXP LOGIC ARRAY CONTROL DELAY tLAC INPUT DELAY tIN LOGIC ARRAY DELAY tLAD
REGISTER OUTPUT DELAY OUTPUT tRD tCOMB tLATCH tOD tXZ tZX
INPUT
tCLR tPRE tRSU tRH
SYSTEM CLOCK DELAY tICS CLOCK DELAY tIC FEEDBACK DELAY tFD I/O DELAY tIO
PIA DELAY tPIA
Figure 1. CY7C342B Internal Timing Model
Document #: 38-03014 Rev. *B
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Design Security
The CY7C342B contains a programmable design security feature that controls the access to the data programmed into the device. If this programmable feature is used, a proprietary design implemented in the device cannot be copied or retrieved. This enables a high level of design control to be obtained since programmed data within EPROM cells is invisible. The bit that controls this function, along with all other program data, may be reset simply by erasing the entire device. The CY7C342B is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield. The erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. The devices also contain on-board logic test circuitry to allow verification of function and AC specification once encapsulated in non-windowed packages.
CY7C342B
Output Drive Current
IO OUTPUT CURRENT (mA) TYPICAL
250 IOL 200 150 100 IOH 50 VCC = 5.0V Room Temp.
0
1
2
3
4
5
VO OUTPUT VOLTAGE (V)
Typical ICC vs. fMAX
400
Timing Considerations
Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay tEXP to the overall delay. Similarly, there is an additional tPIA delay for an input from an I/O pin when compared to a signal from straight input pin. When calculating synchronous frequencies, use tSU if all inputs are on dedicated input pins. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tS1. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the synchronous configuration. When calculating external asynchronous frequencies, use tAS1 if all inputs are on the dedicated input pins. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the asynchronous configuration. The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchronous clock. If tOH is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions.
ICC ACTIVE (mA) Typ.
300
VCC = 5.0V Room Temp.
200
100
0 100 Hz
1 kHz
10 kHz
100 kHz
1 MHz 10 MHz
50 MHz
MAXIMUM FREQUENCY
Document #: 38-03014 Rev. *B
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ -65C to +135C Ambient Temperature with Power Applied............................................ -65C to +135C Maximum Junction Temperature (under bias).................................................................. 150C Supply Voltage to Ground Potential ............-2.0V to +7.0V[1]
CY7C342B
DC Output Current per Pin[1] ................... -25 mA to +25 mA DC Input Voltage[1] .........................................-2.0V to +7.0V
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 5V 5% 5V 10%
Electrical Characteristics Over the Operating Range
Parameter VCC VOH VOL VIH VIL IIX IOZ tR tF Description Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Current Output Leakage Current Recommended Input Rise Time Recommended Input Fall Time VI = VCC or ground VO = VCC or ground Test Conditions Maximum VCC rise time is 10 ms IOH = -4 mA DC[2] IOL = 8 mA DC[2] 2.0 -0.3 -10 -40 Min. 4.75(4.5) 2.4 0.45 VCC + 0.3 0.8 +10 +40 100 100 Max. 5.25(5.5) Unit V V V V V A A ns ns
Capacitance
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 0V, f = 1.0 MHz VOUT = 0V, f = 1.0 MHz Max. 10 20 Unit pF pF
AC Test Loads and Waveforms
R1 464 5V OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 250 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 250 3.0V 10% GND 6 ns R1 464 ALL INPUT PULSES 90% 90% 10% 6 ns
(a)
(b)
Equivalent to: OUTPUT
THEVENIN EQUIVALENT (commercial/military) 163 1.75V
Notes: 1. Minimum DC input is -0.3V. During transactions, input may undershoot to -2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter than 20 ns. 2. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.
Document #: 38-03014 Rev. *B
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CY7C342B
Commercial and Industrial External Synchronous Switching Characteristics Over Operating Range
7C342B-15 Parameter tPD1 tPD2 tSU tCO1 tH tWH tWL fMAX tCNT fCNT Description Dedicated Input to Combinatorial Output Delay I/O Input to Combinatorial Output Delay Global Clock Set-Up Time Synchronous Clock Input to Output Delay Synchronous Clock Input HIGH Time Synchronous Clock Input LOW Time Maximum Register Toggle Frequency Minimum Global Clock Period Maximum Internal Global Clock Frequency[5] 83.3
[4] [3] [3] [3]
7C342B-20 Min. Max. 20 33 13 9 0 7 7 71.4 Unit ns ns ns ns ns ns ns MHz 15 66.7 ns MHZ
Min.
Max. 15 25
10 8 0 5 5 100 12
Input Hold Time from Synchronous Clock Input
Commercial and Industrial External Synchronous Switching Characteristics Over Operating Range
7C342B-25 Parameter tPD1 tPD2 tSU tCO1 tH tWH tWL fMAX tCNT tODH fCNT Description Dedicated Input to Combinatorial Output I/O Input to Combinatorial Output Global Clock Set-Up Time Synchronous Clock Input to Output Delay[3] 0 8 8 62.5 20 2 50 2 40 Frequency[5] Input Hold Time from Synchronous Clock Input Synchronous Clock Input HIGH Time Synchronous Clock Input LOW Time Maximum Register Toggle Frequency[4] Minimum Global Clock Period Output Data Hold Time After Clock Maximum Internal Global Clock Delay[3] 15 14 0 10 10 50 25 2 33.3 Delay[3] Min. Max. 25 40 20 16 0 12.5 12.5 40 30 7C342B-30 Min. Max. 30 45 25 20 7C342B-35 Min. Max. 35 55 Unit ns ns ns ns ns ns ns MHz ns ns MHz
Commercial and Industrial External Asynchronous Switching Characteristics Over Operating Range
7C342B-15 Parameter tACO1 tAS1 tAH tAWH tAWL tACNT fACNT tACO1 tAS1 tAH Description Asynchronous Clock Input to Output Delay[3] Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[6] Input Hold Time from Asynchronous Clock Input Asynchronous Clock Input HIGH Time[6] Asynchronous Clock Input LOW Time[6] Minimum Internal Array Clock Frequency Maximum Internal Array Clock Frequency[5] Asynchronous Clock Input to Output Delay[3] Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[5] Input Hold Time from Asynchronous Clock Input 5 6 83.3 25 6 8 5 5 5 5 12 66.7 30 10 10 Min. Max. 15 6 6 7 7 15 7C342B-20 Min. Max. 20 Unit ns ns ns ns ns ns MHz
Notes: 3. C1 = 35 pF. 4. The fMAX values represent the highest frequency for pipeline data. 5. This parameter is measured with a 16-bit counter programmed into each LAB 6. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped.
Document #: 38-03014 Rev. *B
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7C342B-15 Parameter tAWH tAWL tACNT fACNT Description Asynchronous Clock Input HIGH Time
[5]
CY7C342B
7C342B-20 Min. 14 11 20 50 40 25 33.3 Max. Unit 16 14
Commercial and Industrial External Asynchronous Switching Characteristics Over Operating Range (continued)
Min. 11 9 Max.
Asynchronous Clock Input LOW Time[5] Minimum Internal Array Clock Frequency Maximum Internal Array Clock Frequency[5]
Commercial and Industrial Typical Internal Switching Characteristics Over Operating Range
7C342B-15 Parameter tIN tIO tEXP tLAD tLAC tOD tZX[8] tXZ tRSU tRH tLATCH tRD tCOMB[9] tIC tICS tFD tPRE tCLR tPIA tIN tIO tEXP tLAD tLAC tOD tZX[8] tXZ tRSU tRH tLATCH tRD Description Dedicated Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer and Pad Delay[3] Output Buffer Enable Output Buffer Disable Delay[3] Delay[7] 2 7 1 1 1 6 0 1 3 3 10 5 6 12 12 10 5 10 10 6 4 3 1 8 6 4 2 Min. Max. 3 3 8 8 5 3 5 5 1 10 1 1 1 8 0 1 3 3 13 7 6 14 14 12 5 11 11 10 8 7C342B-20 Min. Max. 4 4 10 12 5 3 5 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Register Set-Up Time Relative to Clock Signal at Register Register Hold Time Relative to Clock Signal at Register Flow Through Latch Delay Register Delay Transparent Mode Delay Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Programmable Interconnect Array Delay Time Dedicated Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer and Pad Delay[3] Output Buffer Enable Output Buffer Disable Delay[3] Delay[7]
Register Set-Up Time Relative to Clock Signal at Register Register Hold Time Relative to Clock Signal at Register Flow Through Latch Delay Register Delay
Notes: 7. C1 = 5 pF. 8. Sample tested only for an output change of 500 mV. 9. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation.
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CY7C342B
Commercial and Industrial Typical Internal Switching Characteristics Over Operating Range (continued)
7C342B-25 Parameter tCOMB[9] tIC tICS tFD tPRE tCLR tPIA Description Transparent Mode Delay Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Programmable Interconnect Array Delay Time Min. Max. 3 14 3 1 5 5 14 7C342B-30 Min. Max. 4 16 2 1 6 6 16 7C342B-35 Min. Max. 4 16 1 2 7 7 20 Unit ns ns ns ns ns ns ns
Switching Waveforms
External Combinatorial
DEDICATED INPUT/ I/O INPUT tPD1/tPD2 COMBINATORIAL OUTPUT
External Synchronous
tWH tWL
SYNCHRONOUS CLOCK PIN SYNCHRONOUS CLOCK AT REGISTER DATA FROM LOGIC ARRAY
tSU
tH
tCO1
REGISTERED OUTPUTS
External Asynchronous
DEDICATED INPUTS OR REGISTERED FEEDBACK tAS1 ASYNCHRONOUS CLOCK INPUT tAH tAWH tAWL
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Switching Waveforms (continued)
Internal Combinatorial
INPUT PIN t IO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT tIN
CY7C342B
LOGIC ARRAY OUTPUT
tCOMB
OUTPUT PIN
tOD
Internal Synchronous
CLOCK FROM LOGIC ARRAY tRD tOD
DATA FROM LOGIC ARRAY tXZ OUTPUT PIN tZX HIGH IMPEDANCE STATE
Internal Asynchronous
tIOR t CLOCK PIN tIN CLOCK INTO LOGIC ARRAY CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY tRD,tLATCH REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY tPIA REGISTER OUTPUT TO ANOTHER LAB tFD tCLR,tPRE tFD tAWH tAWL tF
tIC
tRSU
tRH
Document #: 38-03014 Rev. *B
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Switching Waveforms (continued)
Internal Synchronous
CY7C342B
SYSTEM CLOCK PIN tIN SYSTEM CLOCK AT REGISTER DATA FROM LOGIC ARRAY tICS
tRSU
tRH
Ordering Information
Speed (ns) 15 20 25 Ordering Code CY7C342B-15JC/JI CY7C342B-20JC/JI CY7C342B-25HC/HI CY7C342B-25JC/JI CY7C342B-25RC/RI 30 35 CY7C342B-30JC/JI CY7C342B-35JC/JI CY7C342B-35RJ/RI Package Name J81 J81 H81 J81 R68 J81 J81 R68 Package Type 68-lead Plastic Leaded Chip Carrier 68-lead Plastic Leaded Chip Carrier 68-pin Windowed Leaded Chip Carrier 68-lead Plastic Leaded Chip Carrier 68-pin Windowed Ceramic Pin Grid Array 68-lead Plastic Leaded Chip Carrier 68-lead Plastic Leaded Chip Carrier 68-pin Windowed Ceramic Pin Grid Array Commercial/ Industrial Commercial/ Industrial Operating Range Commercial/ Industrial Commercial/ Industrial Commercial/ Industrial
Document #: 38-03014 Rev. *B
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Package Diagrams
CY7C342B
68-pin Windowed Leaded Chip Carrier H81
51-80080-**
Document #: 38-03014 Rev. *B
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Package Diagrams (continued)
68-lead Plastic Leaded Chip Carrier J81
CY7C342B
51-85005-*A
Document #: 38-03014 Rev. *B
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Package Diagrams (continued)
68-Pin Windowed PGA Ceramic R68
CY7C342B
51-80099-*A
MAX and Warp are registered trademarks and Ultra37000, Warp Professional and Warp Enterprise are trademarks of Cypress Semiconductor Corporation. All product and company ames mentioned in this document are the trademarks of their respective holders.
Document #: 38-03014 Rev. *B
Page 13 of 14
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress.
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Document History Page
Document Title: CY7C342B 128-Macrocell MAX(R) EPLD Document Number: 38-03014 REV. ** *A *B ECN NO. 106314 113612 213375 Issue Date 04/25/01 04/11/02 See ECN Orig. of Change SZV OOR FSG Description of Change Change from Spec number: 38-00119 to 38-03014 PGA package diagram dimensions were updated
CY7C342B
Added note to title page: "Use Ultra37000 For All New Designs"
Document #: 38-03014 Rev. *B
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